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Integrated Circuit Systems, Inc.
ICS9250-09
Frequency Timing Generator for PENTIUM II Systems
General Description
The ICS9250-09 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the ICS9211-01. Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-09 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. The CPU/2 clocks are inputs to the DRCG.
Features
*
Generates the following system clocks: - 4 CPU clocks ( 2.5V, 100/133MHz) - 8 PCI clocks, including 1 free-running (3.3V, 33MHz) - 2 CPU/2 clocks (2.5V, 50/66MHz) - 3 IOAPIC clocks (2.5V, 16.67MHz) - 4 Fixed frequency 66MHz clocks(3.3V, 66MHz) - 2 REF clocks(3.3V, 14.318MHz) - 1 USB clock (3.3V, 48MHz) Efficient power management through PD#, CPU_STOP# and PCI_STOP#. 0.5% typical down spread modulation on CPU, PCI, IOAPIC, 3V66 and CPU/2 output clocks. Uses external 14.318MHz crystal.
* * *
Key Specification
* * * * * * * * * * * * * CPU Output Jitter: <250ps CPU/2 Output Jitter. <250ps IOAPIC Output Jitter: <500ps 48MHz, 3V66, PCI Output Jitter: <500ps Ref Output Jitter. <1000ps CPU Output Skew: <175ps CPU/2 Output Skew. <175ps IOAPIC Output Skew <250ps PCI Output Skew: <500ps 3V66 Output Skew <250ps CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads) 3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads) CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
Pin Configuration
Block Diagram
56-pin SSOP
9250-09 Rev K 10/05/01
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9250-09
Pin Descriptions
Pin number 1 2, 3 4 5 6 7, 13, 19 8 Pin name GNDREF REF(0:1) VDDREF X1 X2 GNDPCI PCICLK_F Type PWR OUT PWR IN OUT PWR OUT OUT PWR PWR OUT PWR IN PWR OUT PWR IN IN Description Gnd pin for REF clocks 14.318MHz reference clock outputs at 3.3V Power pin for REF clocks XTAL_IN 14.318MHz crystal input XTAL_OUT Crystal output Gnd pin for PCICLKs Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected by the PCI_STOP# input. PCI clock outputs at 3.3V. Synchronous to CPU clocks. 3.3Volts power pin for PCICLKs Gnd pin for 3V66 outputs 66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is driven active.. power pin for the 3V66 clocks. This selects the frequency for the CPU and CPU/2 outputs. High = 133MHz, Low=100MHz Ground pin for the 48MHz output Fixed 48MHz clock output. 3.3V Power pin for the 48MHz output. Function select pins. See truth table for details. Enables spread spectrum when active(Low). modulates all the CPU, PCI, IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and 48MHz clocks. 0.5% down spread modulation. This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state. This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at logic "0" when driven active(Low). Does not affect the CPU/2 clocks. This asynchronous input halts the PCICLK[1:7] at logic"0" when driven active(Low). PCICLK_F is not affected by this input. Ground pin for the PLL core Power pin for the PLL core. 3.3V Power pin for the CPUCLKs. 2.5V Ground pin for the CPUCLKs Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state of the SEL 133/100MHz. Ground pin for the CPU/2 clocks. 2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on the state of the SEL 133/100# input pin. Power pin for the CPU/2 clocks. 2.5V Ground pin for the IOAPIC outputs. IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at 16.67MHz. Power pin for the IOAPIC outputs. 2.5V.
9, 11, 12, 14, 15, PCICLK[1:7] 17, 18 10, 16 20, 24 21, 22, 25, 26 23, 27 28 29 30 31 32, 33 34 VDDPCI GND66 3V66[0:3] VDD66 SEL 133/100# GND48 48MHz VDD48 SEL[0:1] SPREAD#
35
PD#
IN
36 37 38 39 43, 47 40, 44 41, 42, 45, 46 48 49, 50 51 52 53, 54, 55 56
CPU_STOP# PCI_STOP# GNDCOR VDDCOR VDDLCPU GNDLCPU CPUCLK[0:3] GNDLCPU/2 CPU/2[0:1] VDDLCPU/2 GNDLIOAPIC IOAPIC[0:2] VDDLIOAPIC
IN IN PWR PWR PWR PWR OUT PWR OUT PWR PWR OUT PWR
2
ICS9250-09
Frequency Select:
SEL 133/100- SEL1 SEL0 # 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 CPU MHz Hi-Z N/A 100.00 100.00 CPU/2 MHz Hi-Z N/A 50.00 50.00 3V66 MHz Hi-Z N/A 66.67 66.67 PCI MHz Hi-Z N/A 33.33 33.33 48 MHz Hi-Z N/A Hi-Z REF MHz Hi-Z N/A 14.318 14.318 N/A 14.318 14.318 IOAPIC MHz Hi-Z N/A 16.67 16.67 Test mode (1) Reserved N/A 16.67 16.67 Comments Tri-state Reserved 48MHz PLL disabled
48 TCLK/TCLK/2 TCLK/4 TCLK/4 TCLK/8 2 N/A N/A N/A N/A N/A 133.32 66.67 66.67 33.33 Hi-Z 133.32 66.67 66.67 33.33 48
TCLK TCLK/16
Note: 1. TCLK is a test clock driven on the x1 input during test mode.
Power Management Features:
CPU_STOP# X 0 0 1 1 PD# 0 1 1 1 1 PCI_STOP# CPUCLK CPU/2 IOAPIC X 0 1 0 1 LOW LOW LOW ON ON LOW ON ON ON ON LOW ON ON ON ON 3V66 LOW LOW LOW ON ON PCI LOW LOW ON LOW ON RE PCI_F 48MF. z H LOW ON ON ON ON LOW ON ON ON ON Osc OF F ON ON ON ON VCOs OFF ON ON ON ON
Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. 4. All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW. 5. CPU/2, IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions except PD# = LOW
3
ICS9250-09
Power Management Requirements:
Latency Singal Singal State 0 (disabled) 1 (enabled) 0 (disabled) 1 (enabled) 1 (normal operation) 0 (power down) No. of rising edges of PCICLK 1 1 1 1 3mS 2max.
CPU_STOP PCI_STOP# PD#
Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
CPU_STOP# Timing Diagram
CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for both the CPU and 3V66 outputs to become enabled/disabled.
Notes:
1. All timing is referenced to the internal CPUCLK. 2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed. 3. CPU_STOP# signal is an input singal that must be made synchronous to free running PCICLK_F 4. 3V66 clocks also stop/start before 5. PD# and PCI_STOP# are shown in a high state. 6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz
4
ICS9250-09
PCI_STOP# Timing Diagram
PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output. It is used to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for the PCI outputs to become enabled/disabled.
Notes: 1. All timing is referenced to CPUCLK. 2. PCI_STOP# signal is an input signal which must be made synchronous to PCICLK_F output. 3. Internal means inside the chip. 4. All other clocks continue to run undisturbed. 5. PD# and CPU_STOP# are shown in a high state. 6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
5
ICS9250-09
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9250 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
6
ICS9250-09
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
G roup O ffset
Group CPU to 3V66 3 V66 to PCI CPU to IOAPIC Offset 0.0-1 .5 ns CPU leads 1.5-4.0n s 3 V66 leads 1.5-4 .0 ns CPU leads Measurem ent Loads CPU @ 20pF, 3V66 @ 30p F 3V66 @ 3 0pF, PCI @ 30pF C PU @ 20p F, IOAPIC @ 2 0pF Measure Po ints C PU @ 1.25V, 3V66 @ 1.5V 3V66 @ 1.5V, PC I @ 1.5V CPU @ 1.25V, IOAPIC @ 1.5V
No te: 1 . All o ffs ets are to b e measu red at risin g ed g es .
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time1 Clk Stabilization 1
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP100 IDD3.3OP133 IDD3.3PD Fi C IN C INX TTrans TS TStab
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Select @ 100MHz; Max discrete cap loads Select @ 133MHz; Max discrete cap loads CL = 0 pF; PWRDWN# = 0 VDD = 3.3 V Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq.
0.1 2.0 -100 68 80 62
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 180 mA uA MHz pF pF ms ms 3 ms
200 16 5 45 3
12 27
14.318 36 1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Operating IDD2.5OP66 Select @ 100MHz; No Load. IDD2.5OP100 Select @ 133MHz; No Load. Supply Current
1
TYP 72 79
MAX 100 100
UNITS mA
Guaranteed by design, not 100% tested in production.
7
ICS9250-09
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute Jitter, Cycle-to-cycle
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B
1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19 0.4 0.4 45
TYP 2.2 0.3 -35 27 1.2 1.25 48 80 20
MAX UNITS V 0.4 V -19 mA mA 1.6 1.6 55 175 150 +250 250 ns ns % ps ps ps ps
d t2B1 tsk2B1 tj12B1 tjabs2B1 tjcyc-cyc2B1
-250
61 150
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU/2
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, One Sigma Jitter, Absolute Jitter, Cycle-to-cycle
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B
1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19 0.4 0.4 45 -250
TYP 2.3 0.3 -35 27 1.1 1 48 20 70 100
MAX UNITS V 0.4 V -19 mA mA 1.6 1.6 55 150 +250 250 ns ns % ps ps ps
tf2B1 d t2B1 tj12B1 tjabs2B1 tjcyc-cyc2B1
Guaranteed by design, not 100% tested in production.
8
ICS9250-09
Electrical Characteristics - 3V66
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tj1 1 tjabs1 tjcyc-cyc1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
25 0.5 0.5 45
TYP 3.1 0.25 -60 44 1.6 1.3 48 120 43
MAX UNITS V 0.4 V -22 mA mA 2 2 55 175 150 250 500 ns ns % ps ps ps ps
Duty Cycle
Jitter, One Sigma
Jitter, Absolute Jitter, Cycle-to-cycle1
1
1
-250
100 150
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tj1 1 tjabs1 tjcyc-cyc1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
25 0.5 0.5 45
TYP 3.1 0.2 -60 45 1.7 1.6 50 360 18
MAX UNITS V 0.4 V -22 mA mA 2 2 55 500 150 250 500 ns ns % ps ps ps ps
Duty Cycle
Jitter, One Sigma
Jitter, Absolute Jitter, Cycle-to-cycle1
1
1
-250
80 155
Guaranteed by design, not 100% tested in production.
9
ICS9250-09
Electrical Characteristics - 48MHz, REF
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tr5 tf5 dt5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V, 48MHz VOH = 2.4 V, VOL = 0.4 V, 48MHz VT = 1.5 V, 48MHz VOL = 0.4 V, VOH = 2.4 V, REF VOH = 2.4 V, VOL = 0.4 V, REF VT = 1.5 V, REF VT = 1.5 V, 48MHz VT = 1.5 V, REF
MIN 2.6
17
TYP 2.9 0.3 -35 23 2 2
MAX UNITS V 0.4 V -22 mA mA 4 4 55 4 4 55 500 1000 ns ns % ns ns % ps ps
Duty Cycle Rise Time Fall Time
1
45
50 2.2 1.9
1
Duty Cycle
1 1
45
52 200 800
Jitter, Cycle-to-cycle Jitter, Cycle-to-cycle1
1
tjcyc-cyc5 tjcyc-cyc5
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH4B VOL4B IOH4B IOL4B Tr4B Tf4B Dt4B Tj1 4B Tjabs4B
tjcyc-cyc4B
CONDITIONS IOH = -12 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19 0.4 0.4 45 -250
TYP 2.23 0.3 -36 26 1.3 1.25 49 14 65
87
MAX UNITS V 0.4 V -16 mA mA 1.6 1.6 55 150 250
500
ns ns % ps ps
ps
Duty Cycle
Jitter, One Sigma
Jitter, Absolute Jitter, Cycle-to-cycle1
1
1
Guaranteed by design, not 100% tested in production.
10
ICS9250-09
General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. 2) Make all power traces and ground traces as wide as the via pad for lower inductance.
Ferrite Bead VDD
C2 22F/20V Tantalum
C2 22F/20V Tantalum
Ferrite Bead VDD
1 2 3 4
C1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
3.3V Power Route 1 C3 Clock Load 2.5V Power Route
5 6 7 8 9 10 11 12
Notes: 1 All clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. 2 Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed.
C1 2
3.3V Power Route
13 14 15 16 17 18 19
Connections to VDD:
20 21 22 23 24 25 26 27 28
= Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load
11
ICS9250-09
Pin 1 D/2 .093 DIA. PIN (Optional)
Index Area
E/2
PARTING LINE
H L DETAIL "A" BOTTOM VIEW -eA2 SEE DETAIL "A" c -E-DEND VIEW A1 B A
.004 C
TOP VIEW
SEATING PLANE -C-
SIDE VIEW
SYMBOL A A1 A2 B c D E e H h L N
COMMON DIMENSIONS MIN. NOM. MAX. .095 .102 .110 .008 .012 .016 .087 .090 .094 .008 .0135 .005 .010 See Variations .291 .295 .299 0.025 BSC .395 .420 .010 .013 .016 .020 .040 See Variations 0 8
VARIATIONS AD MIN. .720
D NOM. .725
N MAX. .730 56
"For current dimensional specifications, see JEDEC 95."
Dimensions in inches
56 Pin 300 mil SSOP Package Ordering Information
ICS9250yF-09-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
12
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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